This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-186606, filed Jun. 20, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a power semiconductor device having a MISFET (metal insulator semiconductor field effect transistor) and a rectifying element mounted on the same semiconductor chip, and a semiconductor device for use in, e.g., a direct-current switch or a DCxe2x80x94DC converter.
2. Description of the Related Art
As a power MISFET (MOSFET), there is known an FET having a double diffusion type lateral structure, a P-channel type FET (PMOSFET) having an LDD (lightly-doped drain) structure or an N-channel type FET (NMOSFET), for example. The performance of these FETs is improved (reducing losses) by adopting the structure that a plurality of FET cells are aligned on a semiconductor substrate.
As an example of use of the power MOSFET, there is a direct-current switch which is inserted in a drive current supply path between a direct-current supply and a load (for example, a motor or an LSI).
FIG. 1 shows an example of the circuit connection using a direct-current switch constituted by connecting a conventional PMOSFET and a reverse current preventing diode in series.
In this circuit, a diode is inserted in the forward direction between the direct-current supply 81 and the load 82, and a source and a drain of the PMOSFET 84 are inserted in series. In this case, as a diode, there is usually used a Schottky barrier diode (SBD) 83 which has the high-speed responsibility and whose voltage drop and steady loss is small.
It is to be noted that a parasitic PN junction diode 85 exists in the reverse direction between the drain and source of the PMOSFET 84. Further, a battery 86 is connected to the load 82 in parallel.
In the circuit illustrated in FIG. 1, a pulse signal for switching control is applied between a gate of the PMOSFET 84 and the ground potential GND. When the PMOSFET 84 is controlled in the ON state, a drive current is supplied from the direct-current supply 81 toward the load 82 through the part between an anode and a cathode of the SBD 83 and the PMOSFET 84. In this period, the battery 86 is charged.
Then, in the OFF period of the PMOSFET 84, when the reverse current starts to flow from the battery 86 toward the direct-current supply 81 through the parasitic PN junction diode 85 of the PMOSFET 84, the reverse junction between the cathode and the anode of the SBD 83 avoids the reverse current.
Meanwhile, when assembling a product in which the PMOSFET 84 and the SBD 83 are formed on different chips and accommodated in different packages, there is a problem that the degree of freedom in development and design is restricted in terms of a packaging area (occupied space) or the like.
Furthermore, when the PMOSFET 84 and the SBD 83 are formed on different chips and mounted on a lead frame in the electrically insulated state, the source of the PMOSFET 84 and the cathode of the SBD 83 must be connected by using external wirings (for example, they are connected to the lead frame by using wire bonding), which leads to a problem that the resistance component or the inductance component of the entire circuit increases.
Moreover, FIG. 2 shows a conventional DCxe2x80x94DC converter of a synchronous rectification type which is constituted by using an NMOSFET and a diode. In this circuit, although the NMOSFET 91 and the diode 92 are connected in parallel, an SBD is usually likewise used for the diode in this case. In FIG. 2, it is to be noted that reference numeral 93 denotes an NMOSFET for switching and 94 designates a control IC (integrated circuit) which controls the NMOSFET 91 and the element 93.
Meanwhile, when assembling a product in which the NMOSFET 91 (or 93) and the SBD 92 are formed on different chips and accommodated in different packages, the cost, the packaging area or the like is restricted. When they are formed on different chips and packaged on the lead frame in the electrically insulated state, there is a problem similar to that in the prior art circuit of FIG. 1, namely, the resistance component or the inductance component of the entire circuit increases due to the external wiring.
As described above, the prior art semiconductor device having the MOSFET and the SBD connected in series by using the external wiring has a problem that the cost, the packaging area and the resistance component or the inductance component of the wiring increase.
Therefore, in the semiconductor device having the FET and the diode mounted on the same chip, there has been long-awaited a semiconductor device which can eliminate the need of connecting the source area of the FET and the cathode of the diode through the external wirings and reduce the cost, the packaging area, and the resistance component or the inductance component of the wirings.
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
a first conductivity type semiconductor substrate having a first and a second main plane:
a first conductivity type semiconductor layer formed on the first main plane of the semiconductor substrate;
a MISFET formed in a first surface area of the semiconductor layer, the MISFET having a drain region and a source region selectively formed on the semiconductor layer, and a gate electrode formed on the semiconductor layer between the drain region and the source region through a gate insulator;
an internal source electrode formed so as to contact the source region on a top of the semiconductor layer and whose surface is covered with an insulating layer;
a diode formed in a second surface area of the semiconductor layer, the diode having a cathode region provided in the semiconductor layer and an anode region provided on the cathode region;
an anode electrode formed above the semiconductor layer and contacts the anode region of the diode;
a conductive portion which pierces the semiconductor layer so as to electrically connect the internal source electrode of the MISFET and the cathode region of the diode to the semiconductor substrate; and
a source/cathode electrode formed on the second main plane of the semiconductor substrate and commonly provided as a source electrode of the MISFET and a cathode electrode of the diode.
According to a second aspect of the present invention, there is provided a semiconductor device comprising:
a first conductivity type semiconductor substrate having a first and a second main plane;
a first conductivity type semiconductor layer formed on the first main plane of the semiconductor substrate;
a plurality of MISFETs formed in a first surface area of the semiconductor layer, each of the plurality of MISFETs having a drain region and a source region selectively formed on the semiconductor layer, and a gate electrode formed on the semiconductor layer between the drain region and the source region through a gate insulator;
an internal drain electrode formed so as to contact the drain region on the semiconductor layer;
an internal source electrode formed so as to contact the source region on the semiconductor layer;
a diode formed in the second surface area of the semiconductor layer, the diode having a cathode region provided in the semiconductor layer and an anode region provided on the cathode region;
an anode electrode formed above the semiconductor layer and contacts the anode region of the diode;
an interlayer insulator formed on the first semiconductor layer so as to cover the first surface area and the second surface area while exposing the anode electrode;
a surface drain electrode formed on the interlayer insulator above the first surface area and connected to the internal drain electrode of each of the plurality of MISFETs;
a conductive portion which pierces the semiconductor layer so as to electrically connect the internal source electrode of the MISFET and the cathode area of the diode; and
a source/cathode electrode formed on the second main plane of the semiconductor substrate and commonly provided as a source electrode of the plurality of MISFETs and a cathode electrode of the diode.
According to a third aspect of the present invention, there is provided a semiconductor device comprising:
a first conductivity type semiconductor substrate having a first and a second main plane;
a first conductivity type semiconductor layer formed on the first main plane of the semiconductor substrate;
a plurality of MISFETs formed in the semiconductor layer, each of the plurality of MISFETs having a drain region and a source region selectively formed on the semiconductor layer, and a gate electrode formed on the semiconductor layer between the drain region and the source region through a gate insulator;
an internal drain electrode formed so as to contact the drain region on the semiconductor layer;
an internal source electrode formed so as to contact the source region on the semiconductor layer;
a plurality of diodes formed in areas between the plurality of MISFETs on the semiconductor layer, each of the plurality of diodes having a cathode region provided in the semiconductor layer and an anode region provided on the cathode region;
a plurality of internal anode electrodes formed above the semiconductor layer and contact the anode region of each of the plurality of diodes;
an interlayer insulator formed on the first semiconductor layer;
a surface drain electrode formed on the interlayer insulator and connected to the internal drain electrode of each of the plurality of MISFETs;
a surface anode electrode formed on the interlayer insulator and connected to the plurality of internal anode electrodes;
a plurality of conductive portions which pierce the semiconductor layer so as to electrically connect the internal source electrode of each of the plurality of MISFETs and the cathode region of each of the plurality of diodes to the semiconductor substrate; and
a source/cathode electrode formed on the second main plane of the semiconductor substrate and commonly provided as a source electrode of the plurality of MISFETs and a cathode electrode of the plurality of diodes.